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March 28, 2022

New Chip-Scale Interconnect Advancements to Boost Processing Including 8K Ecosystem

There’s a saying that the number of people forecasting the end of Moore’s Law doubles every two years. While we may indeed be reaching the limits of this law, the improvements have been harder to achieve and have cost more and more with each generation. So, companies are looking at alternative ways to significantly boost the performance of semiconductors as the size of the features start to get down to the size of single atoms. There have been several exciting developments in this area in the last few weeks.

Interestingly, this point was forecast by Gordon Moore in his original paper when he said that there would be a ‘Day of Reckoning’. “It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected,” he is quoted as saying.

The first development was that a group of prominent chip designers and makers announced a new approach to allow a better way to combine smaller chips (“chiplets”) from different vendors into single devices. The Consortium is backed by Intel, AMD, Arm, Qualcomm, Samsung, Google, Meta, Microsoft, and chipmakers TSMC and ASE. Notable by their absence were Apple and Nvidia. But since the announcement of the initiative, those companies have also said more about what they are doing.

Chiplet - Chip-Scale Interconnect Advancements

The UCIe Initiative

The new industry initiative is called the Universal Chiplet Interconnect Express (or UCIe). It is based around the idea of breaking up the huge monolithic CPUs, GPUs and SoCs into smaller parts allowing them to be re-arranged to optimise performance. Bob O’Donnell, an established industry analyst, pointed out that this is a bit like how Arm introduced the idea of “Big.little”. The idea is to connect differing CPU cores in such a way to reduce power consumption and optimize operation. That idea has been very widely adopted.

Systems on Chip (SOCs) combine different elements with different strengths (CPUs, GPUs, signal processors, video processors, modems, etc.) onto a single big chip. That’s the kind of chip that you can get from vendors, including Qualcomm or Mediatek. However, these big chips are made in a single fab using the same manufacturing processes, which is not necessarily ideal. You can genuinely benefit from the latest 4nm node process technology for some functions. Other parts of the chip might be better off with larger features. In addition, it might be cheaper to only use the most advanced processes only for some parts of the chip.[CC1] 

Opportunities for Specialisms

Of course, not every chip maker has designs and technology of the same type or level of performance. How cool would it be to ‘mix and match’ the best (or best for your application, or lowest powered or cheapest) components? As O’Donnell said, you might want to mix “an AMD GPU, a Qualcomm modem, a Google TPU AI accelerator and a Microsoft Pluton security processor onto a single chip package”. UCIe should allow you to do that, with products being commercialised within two to three years, the Consortium believes.

Companies could design highly optimised ‘chiplets’ while others could develop complete system chips based on knowledge of how to combine components from different makers. That should open up the industry to a wider range of smaller companies rather than just the juggernauts that can currently develop the huge chips we now have.

The UCIe Consortium provided this chart in its downloadable white paper

Figure 2: Design cost across different process nodes (Source: IBS, as cited in IEEE Heterogeneous Integration Roadmap)

Yole Development recently reported that Intel is the biggest spender in the $11.6 billion invested in chip packaging last year, with $3.5 billion (30%), followed by TSMC at $3.05 billion (26%). ASE is at $2 billion, closely followed by Samsung.

Source: Yole Development: The company has released a lot of information on the interconnect and chip packaging market here.

Second Development: Apple Goes its Own Way

A sense of why Apple might not be involved in the Consortium was revealed when the firm announced its M1 Ultra chip, which, the firm said, uses a silicon interposer that sits between two of its M1 chips to create a device with close to twice the power. Apple calls the technology to join the two chips ‘UltraFusion’, enabling 10,000 connection points between the two chips. The connector is said to use very little power, has low latency and can provide 2.5TBps of bandwidth.

Tim Bajarin, writing for Forbes, pointed out that this kind of 2.5D connection was pioneered by TSMC (Apple’s chip-making partner) and Xilinx (which has just been acquired by AMD. The Apple concept is more power-efficient than if it designed a single big chip.

Apple, of course, as well as having this solution, has the money, power and design skills not to have to worry about the challenges that smaller companies face.


Nvidia was one of the companies not part of the initial announcement as a supporter of UCIe. However, this week the firm announced its new 4nm architecture-based Hopper chip architecture and a separate ‘Lovelace’ architecture for consumer GPUs.  Nvidia’s Jensen Huang said, “As soon as the UCIe spec is stabilized, we’ll put it into our chips as fast as we can”.

“It will take, as it did with PCI Express, about half a decade or so”, Huang believes. “UCIe has the benefit of allowing us to connect many things to our chips and now allow us to connect our chips to many things”.

The support by Nvidia means that it is feasible that, in the future, companies could combine, for example, Intel CPUs with Nvidia GPUs.

Separately, Nvidia said last week that it has its own ultra-fast chip-to-chip and die-to-die interconnect called NVLink-C2C. It is said to be 90x more area-efficient than PCIe Gen 5 on Nvidia chips and to enable coherent interconnect bandwidth of 900 gigabytes-per second or higher.

Why Should the 8K Association Care?

You might be wondering why the 8KA should care about this topic? Well, first, 8K means more and more data is processed. 8K will be enabled by the newer and better codecs that reduce the data transmitted within and between content creators, distributors and displays. More effective compression typically means a trade-off with more complexity in the encoders and decoders (a topic we are beavering away on in the background). Producing that processing complexity with higher performance and lower cost will be a central part of enabling the 8K ecosystem.

As UCIe gets closer to introduction, we would expect to see more ideas on how the technology could be exploited to help drive 8K adoption.

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